instruction set architecture for other uses of isa see isa disambiguation machine code general concepts instruction set opcode illegal opcode opcode prefix opcode table operand instructions nop branch indirect branch vte an instruction set architecture isa is an abstract model of a computer it is also referred to as architecture or computer architecture a realization of an isa is called an implementation an isa permits multiple implementations that may vary in performance physical size and monetary cost among other things because the isa serves as the interface between software and hardware software that has been written for an isa can run on different implementations of the same isa this has enabled binary compatibility between different generations of computers to be easily achieved and the development of computer families both of these developments have helped to lower the cost of computers and to increase their applicability for these reasons the isa is one of the most important abstractions in computing today an isa defines everything a machine language programmer needs to know in order to program a computer what an isa defines differs between isas in general isas define the supported data types what state there is such as the main memory and registers and their semantics such as the memory consistency and addressing modes the instruction set the set of machine instructions that comprises a computers machine language and the inputoutput model overview an instruction set architecture is distinguished from a microarchitecture which is the set of processor design techniques used in a particular processor to implement the instruction set processors with different microarchitectures can share a common instruction set for example the intel pentium and the advanced micro devices athlon implement nearly identical versions of the x86 instruction set but have radically different internal designs the concept of an architecture distinct from the design of a specific machine was developed by fred brooks at ibm during the design phase of system360 prior to npl p137 some virtual machines that support bytecode as their isa such as smalltalk the java virtual machine and microsofts common language runtime implement this by translating the bytecode for commonly used code paths into native machine code in addition these virtual machines execute less frequently used code paths by interpretation see justintime compilation transmeta implemented the x86 instruction set atop vliw processors in this fashion classification of isas an isa may be classified in a number of different ways a common classification is by architectural complexity a complex instruction set computer cisc has many specialized instructions some of which may only be rarely used in practical programs a reduced instruction set computer risc simplifies the processor by efficiently implementing only the instructions that are frequently used in programs while the less common operations are implemented as subroutines having their resulting additional processor execution time offset by infrequent use other types include very long instruction word vliw architectures and the closely related long instruction word liw and explicitly parallel instruction computing epic architectures these architectures seek to exploit instructionlevel parallelism with less hardware than risc and cisc by making the compiler responsible for instruction issue and scheduling architectures with even less complexity have been studied such as the minimal instruction set computer misc and one instruction set computer oisc these are theoretically important types but have not been commercialized instructions machine language is built up from discrete statements or instructions on the processing architecture a given instruction may specify particular registers for arithmetic addressing or control functions particular memory locations or offsets particular addressing modes used to interpret the operands more complex operations are built up by combining these simple instructions which are executed sequentially or as otherwise directed by control flow instructions instruction types examples of operations common to many instruction sets include data handling and memory operations set a register to a fixed constant value copy data from a memory location to a register or vice versa a machine instruction is often called move however the term is misleading used to store the contents of a register result of a computation or to retrieve stored data to perform a computation on it later often called load and store operations read and write data from hardware devices arithmetic and logic operations add subtract multiply or divide the values of two registers placing the result in a register possibly setting one or more condition codes in a status register increment decrement in some isas saving operand fetch in trivial cases perform bitwise operations eg taking the conjunction and disjunction of corresponding bits in a pair of registers taking the negation of each bit in a register compare two values in registers for example to see if one is less or if they are equal floatingpoint instructions for arithmetic on floatingpoint numbers control flow operations branch to another location in the program and execute instructions there conditionally branch to another location if a certain condition holds indirectly branch to another location call another block of code while saving the location of the next instruction as a point to return to coprocessor instructions loadstore data to and from a coprocessor or exchanging with cpu registers perform coprocessor operations complex instructions processors may include complex instructions in their instruction set a single complex instruction does something that may take many instructions on other computers such instructions are typified by instructions that take multiple steps control multiple functional units or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor some examples of complex instructions include transferring multiple registers to or from memory especially the stack at once moving large blocks of memory eg string copy or dma transfer complicated integer and floatingpoint arithmetic eg square root or transcendental functions such as logarithm sine cosine etc simd instructions a single instruction performing an operation on many homogeneous values in parallel possibly in dedicated simd registers performing an atomic testandset instruction or other readmodifywrite atomic instruction instructions that perform alu operations with an operand from memory rather than a register complex instructions are more common in cisc instruction sets than in risc instruction sets but risc instruction sets may include them as well risc instruction sets generally do not include alu operations with memory operands or instructions to move large blocks of memory but most risc instruction sets include simd or vector instructions that perform the same arithmetic operation on multiple pieces of data at the same time simd instructions have the ability of manipulating large vectors and matrices in minimal time simd instructions allow easy parallelization of algorithms commonly involved in sound image and video processing various simd implementations have been brought to market under trade names such as mmx 3dnow and altivec parts of an instruction one instruction may have several fields which identify the logical operation and may also include source and destination addresses and constant values this is the mips add immediate instruction which allows selection of source and destination registers and inclusion of a small constant on traditional architectures an instruction includes an opcode that specifies the operation to perform such as add contents of memory to registerand zero or more operand specifiers which may specify registers memory locations or literal data the operand specifiers may have addressing modes determining their meaning or may be in fixed fields in very long instruction word vliw architectures which include many microcode architectures multiple simultaneous opcodes and operands are specified in a single instruction some exotic instruction sets do not have an opcode field such as transport triggered architectures tta only operands the forth virtual machine and other 0operand instruction sets lack any operand specifier fields such as some stack machines including nosc conditional instructions often have a predicate fielda few bits that encode the specific condition to cause the operation to be performed rather than not performed for example a conditional branch instruction will be executed and the branch taken if the condition is true so that execution proceeds to a different part of the program and not executed and the branch not taken if the condition is false so that execution continues sequentially some instruction sets also have conditional moves so that the move will be executed and the data stored in the target location if the condition is true and not executed and the target location not modified if the condition is false similarly ibm zarchitecture has a conditional store instruction a few instruction sets include a predicate field in every instruction this is called branch predication number of operands instruction sets may be categorized by the maximum number of operands explicitly specified in instructions in the examples that follow a b and c are direct or calculated addresses referring to memory cells while reg1 and so on refer to machine registers c ab 0operand zeroaddress machines so called stack machines all arithmetic operations take place using the top one or two positions on the stack push a push b add pop c c ab needs four instructions for stack machines the terms 0operand and zeroaddress apply to arithmetic instructions but not to all instructions as 1operand push and pop instructions are used to access memory 1operand oneaddress machines so called accumulator machines include early computers and many small microcontrollers most instructions specify a single right operand that is constant a register or a memory location with the implicit accumulator as the left operand and the destination if there is one load a add b store c c ab needs three instructions 2operand many cisc and risc machines fall under this category cisc move a to c then add b to c c ab needs two instructions this effectively stores the result without an explicit store instruction cisc often machines are limited to one memory operand per instruction load areg1 add breg1 store reg1c this requires a loadstore pair for any memory movement regardless of whether the add result is an augmentation stored to a different place as in c ab or the same memory location a ab c ab needs three instructions risc requiring explicit memory loads the instructions would be load areg1 load breg2 add reg1reg2 store reg2c c ab needs four instructions 3operand allowing better reuse of data cisc it becomes either a single instruction add abc c ab needs one instruction cisc or on machines limited to two memory operands per instruction move areg1 add reg1bc c ab needs two instructions risc arithmetic instructions use registers only so explicit 2operand loadstore instructions are needed load areg1 load breg2 add reg1reg2reg3 store reg3c c ab needs four instructions unlike 2operand or 1operand this leaves all three values a b and c in registers available for further reuse more operandssome cisc machines permit a variety of addressing modes that allow more than 3 operands registers or memory accesses such as the vax poly polynomial evaluation instruction due to the large number of bits needed to encode the three registers of a 3operand instruction risc architectures that have 16bit instructions are invariably 2operand designs such as the atmel avr ti msp430 and some versions of arm thumb risc architectures that have 32bit instructions are usually 3operand designs such as the arm avr32 mips power isa and sparc architectures each instruction specifies some number of operands registers memory locations or immediate values explicitly some instructions give one or both operands implicitly such as by being stored on top of the stack or in an implicit register if some of the operands are given implicitly fewer operands need be specified in the instruction when a destination operand explicitly specifies the destination an additional operand must be supplied consequently the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation the arity operands are either encoded in the opcode representation of the instruction or else are given as values or addresses following the instruction register pressure register pressure measures the availability of free registers at any point in time during the program execution register pressure is high when a large number of the available registers are in use thus the higher the register pressure the more often the register contents must be spilled into memory increasing the number of registers in an architecture decreases register pressure but increases the cost while embedded instruction sets such as thumb suffer from extremely high register pressure because they have small register sets generalpurpose risc isas like mips and alpha enjoy low register pressure cisc isas like x8664 offer low register pressure despite having smaller register sets this is due to the many addressing modes and optimizations such as subregister addressing memory operands in alu instructions absolute addressing pcrelative addressing and registertoregister spills that cisc isas offer instruction length the size or length of an instruction varies widely from as little as four bits in some microcontrollers to many hundreds of bits in some vliw systems processors used in personal computers mainframes and supercomputers have instruction sizes between 8 and 64 bits the longest possible instruction on x86 is 15 bytes 120 bits within an instruction set different instructions may have different lengths in some architectures notably most reduced instruction set computers risc instructions are a fixed length typically corresponding with that architectures word size in other architectures instructions have variable length typically integral multiples of a byte or a halfword some such as the arm with thumbextension have mixed variable encoding that is two fixed usually 32bit and 16bit encodings where instructions can not be mixed freely but must be switched between on a branch or exception boundary in armv8 a risc instruction set normally has a fixed instruction length often 4 bytes 32 bits whereas a typical cisc instruction set may have instructions of widely varying length 1 to 15 bytes for x86 fixedlength instructions are less complicated to handle than variablelength instructions for several reasons not having to check whether an instruction straddles a cache line or virtual memory page boundary for instance and are therefore somewhat easier to optimize for speed code density in early computers memory was expensive so minimizing the size of a program to make sure it would fit in the limited memory was often central thus the combined size of all the instructions needed to perform a particular task the code density was an important characteristic of any instruction set computers with high code density often have complex instructions for procedure entry parameterized returns loops etc therefore retroactively named complex instruction set computers cisc however more typical or frequent cisc instructions merely combine a basic alu operation such as add with the access of one or more operands in memory using addressing modes such as direct indirect indexed etc certain architectures may allow two or three operands including the result directly in memory or may be able to perform functions such as automatic pointer increment etc softwareimplemented instruction sets may have even more complex and powerful instructions reduced instructionset computers risc were first widely implemented during a period of rapidly growing memory subsystems they sacrifice code density to simplify implementation circuitry and try to increase performance via higher clock frequencies and more registers a single risc instruction typically performs only a single operation such as an add of registers or a load from a memory location into a register a risc instruction set normally has a fixed instruction length whereas a typical cisc instruction set has instructions of widely varying length however as risc computers normally require more and often longer instructions to implement a given task they inherently make less optimal use of bus bandwidth and cache memories certain embedded risc isas like thumb and avr32 typically exhibit very high density owing to a technique called code compression this technique packs two 16bit instructions into one 32bit instruction which is then unpacked at the decode stage and executed as two instructions minimal instruction set computers misc are a form of stack machine where there are few separate instructions 1664 so that multiple instructions can be fit into a single machine word these types of cores often take little silicon to implement so they can be easily realized in an fpga or in a multicore form the code density of misc is similar to the code density of risc the increased instruction density is offset by requiring more of the primitive instructions to do a task there has been research into executable compression as a mechanism for improving code density the mathematics of kolmogorov complexity describes the challenges and limits of this representation the instructions constituting a program are rarely specified using their internal numeric form machine code they may be specified by programmers using an assembly language or more commonly may be generated from programming languages by compilers design the design of instruction sets is a complex issue there were two stages in history for the microprocessor the first was the cisc complex instruction set computer which had many different instructions in the 1970s however places like ibm did research and found that many instructions in the set could be eliminated the result was the risc reduced instruction set computer an architecture that uses a smaller set of instructions a simpler instruction set may offer the potential for higher speeds reduced processor size and reduced power consumption however a more complex set may optimize common operations improve memory and cache efficiency or simplify programming some instruction set designers reserve one or more opcodes for some kind of system call or software interrupt for example mos technology 6502 uses 00h zilog z80 uses the eight codes c7cfd7dfe7eff7ffh while motorola 68000 use codes in the range a000afffh fast virtual machines are much easier to implement if an instruction set meets the popek and goldberg virtualization requirements the nop slide used in immunityaware programming is much easier to implement if the unprogrammed state of the memory is interpreted as a nop on systems with multiple processors nonblocking synchronization algorithms are much easier to implement if the instruction set includes support for something such as fetchandadd loadlinkstoreconditional llsc or atomic compareandswap instruction set implementation any given instruction set can be implemented in a variety of ways all ways of implementing a particular instruction set provide the same programming model and all implementations of that instruction set are able to run the same executables the various ways of implementing an instruction set give different tradeoffs between cost performance power consumption size etc when designing the microarchitecture of a processor engineers use blocks of hardwired electronic circuitry often designed separately such as adders multiplexers counters registers alus etc some kind of register transfer language is then often used to describe the decoding and sequencing of each instruction of an isa using this physical microarchitecture there are two basic ways to build a control unit to implement this description although many designs use middle ways or compromises some computer designs hardwire the complete instruction set decoding and sequencing just like the rest of the microarchitecture other designs employ microcode routines or tables or both to do thistypically as onchip roms or plas or both although separate rams and roms have been used historically the western digital mcp1600 is an older example using a dedicated separate rom for microcode some designs use a combination of hardwired design and microcode for the control unit some cpu designs use a writable control storethey compile the instruction set to a writable ram or flash inside the cpu such as the rekursiv processor and the imsys cjip or an fpga reconfigurable computing an isa can also be emulated in software by an interpreter naturally due to the interpretation overhead this is slower than directly running programs on the emulated hardware unless the hardware running the emulator is an order of magnitude faster today it is common practice for vendors of new isas or microarchitectures to make software emulators available to software developers before the hardware implementation is ready often the details of the implementation have a strong influence on the particular instructions selected for the instruction set for example many implementations of the instruction pipeline only allow a single memory load or memory store per instruction leading to a loadstore architecture risc for another example some early ways of implementing the instruction pipeline led to a delay slot the demands of highspeed digital signal processing have pushed in the opposite directionforcing instructions to be implemented in a particular way for example to perform digital filters fast enough the mac instruction in a typical digital signal processor dsp must use a kind of harvard architecture that can fetch an instruction and two data words simultaneously and it requires a singlecycle multiplyaccumulate multiplier computer science portal comparison of instruction set architectures computer architecture cpu design emulator simulator list of instruction sets instruction set simulator ovpsim full systems simulator providing ability to createmodelemulate any instruction set using c and standard apis register transfer language rtl microoperation bowen jonathan p julyaugust 1985 standard microprocessor programming cards 9 6 274290 doi1010160141933185901164 the wikibook microprocessor design has a page on the topic of instruction set architectures programming textfiles bowens instruction summary cards mark smothermans historical computer designs page vteprocessor technologiesmodels turing machine universal postturing quantum belt machine stack machine finitestate machine with datapath hierarchical queue automaton register machines counter pointer randomaccess randomaccess stored program architecture von neumann harvard modified dataflow transporttriggered cellular endianness memory access numa huma loadstore registermemory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction setarchitecturestypes cisc risc applicationspecific edge trips vliw epic misc oisc nisc zisc comparison addressing modes x86 arm mips power powerpc sparc itanium unicore microblaze riscv othersexecutioninstruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing outoforder tomasulo algorithm reservation station reorder buffer register renaming speculative branch prediction memory dependence prediction parallelismlevel bit bitserial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynns taxonomy sisd simd swar simt misd mimd spmd processorperformance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floatingpoint operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream coprocessor asic fpga cpld multichip module mcm system in package sip by application microprocessor microcontroller mobile notebook ultralowvoltage asip systemson chip systemonchip soc multiprocessor mpsoc programmable psoc networkonchip noc hardwareaccelerators ai accelerator vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1bit 2bit 4bit 8bit 16bit 32bit 48bit 64bit 128bit 256bit 512bit others variable core count singlecore multicore manycore heterogeneous architecture components core cache cpu cache replacement policies coherence bus clock rate fifo functional units arithmetic logic unt alu address generation unit agu floatingpoint unit fpu memory management unit loadstore unit translation lookaside buffer tlb logic combinational sequential glue logic gate quantum array registers processor register register file memory buffer program counter stack control unit instruction unit data buffer write buffer microcode rom counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch powermanagement pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of generalpurpose cpus microprocessor chronology processor design digital electronics hardware security module authority control gnd 41299310 