system on a chip the raspberry pi uses a system on a chip as an almost fully contained microcomputer this soc does not contain any kind of data storage which is common for a microprocessor soc a system on a chip or system on chip soc sosi esohsee or sk sock systems on chip are commonly used in embedded systems and the internet of things systems on chip are in contrast to the common traditional motherboardbased pc architecture which separates components based on function and connects them through a central interfacing circuit board randomaccess and readonly memories and secondary storage on a single circuit die whereas a motherboard would connect these modules as discrete components or expansion cards more tightly integrated computer system designs improve performance and reduce power consumption as well as semiconductor die area needed for an equivalent design composed of discrete modules at the cost of reduced replaceability of components by definition soc designs are fully or nearly fully integrated across different component modules for these reasons there has been a general trend towards tighter integration of components in the computer hardware industry in part due to the influence of socs and lessons learned from the mobile and embedded computing markets systemsonchip can be viewed as part of a larger trend towards embedded computing and hardware acceleration an soc integrates a microcontroller or microprocessor with advanced peripherals like graphics processing unit gpu wifi module or one or more coprocessors similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory an soc can be seen as integrating a microcontroller with even more advanced peripherals for an overview of integrating system components see system integration types microcontrollerbased system on a chipin general there are four distinguishable types of socs socs built around a microcontroller c socs built around a microprocessor p often found in mobile phones specialized socs designed for specific applications that do not fit into the above two categories and programmable systemsonchip psoc where most functionality is fixed but some functionality is reprogrammable in a manner analogous to a fieldprogrammable gate array amd am286zxlx soc based on intel 80286 applications systemsonchip can be applied to any computing task however they are typically used in mobile computing such as tablets smartphones smartwatches and netbooks as well as embedded systems and in applications where previously microcontrollers would be used embedded systems where previously only microcontrollers could be used socs are rising to prominence in the embedded systems market tighter system integration offers better reliability and mean time between failure and socs offer more advanced functionality and computing power than microcontrollers data collection telemetry vector processing and ambient intelligence often embedded systemsonchip target the internet of things industrial internet of things and edge computing markets mobile computing mobile computing based socs typically bundle processors memories onchip caches wireless networking capabilities and often digital camera hardware and firmware some mobile computing socs include apple appledesigned processors a12 bionic and other a series used in iphones and ipads s series and w series in apple watches apple t series used in the 2016 and 2017 macbook pro touch bars and fingerprint scanners samsung electronics list typically based on arm7 and arm9 exynos used mainly by samsungs galaxy series of smartphones qualcomm snapdragon list used in many lg xiaomi google pixel htc and samsung galaxy smartphones in 2018 snapdragon socs are being used as the backbone of laptop computers running windows 10 marketed as always connected pcs personal computers systemsonchip are being applied to personal computers as of 2018 arm based qualcomm snapdragon x86 based intel pentium gold 4415y used in the microsoft surface go structure an soc consists of hardware functional units including microprocessors that run software code as well as a communications subsystem to connect control direct and interface between these functional modules functional components processor cores an soc must have at least one processor core but will typically have more processor cores can be a microcontroller microprocessor p asips have instruction sets that are customized for an application domain and designed to be more efficient than generalpurpose instructions for a specific type of workload multiprocessor socs have more than one processor core by definition whether singlecore multicore or manycore soc processor cores typically use risc instruction set architectures risc architectures are advantageous over cisc processors for systemsonchip because they require less digital logic and therefore less power and area on board and in the embedded and mobile computing markets these are often highly constrained in particular soc processor cores often use the arm architecture because it is a soft processor specified as an ip core and more power efficient than x86 memories further information computer memory systemsonchip must have semiconductor memory blocks to perform their computation as do microcontrollers and other embedded systems depending on the application soc memory may form a memory hierarchy and cache hierarchy in the mobile computing market this is common but in many lowpower embedded microcontrollers this is not necessary memory technologies for socs include readonly memory rom randomaccess memory ram electrically erasable programmable rom eeprom and flash memory for further discussion of multiprocessing memory issues see cache coherence and memory latency interfaces socs include external interfaces typically for communication protocols these are often based upon industry standards such as usb firewire ethernet usart spi hdmi ic etc these interfaces will differ according to the intended application wireless networking protocols such as wifi bluetooth 6lowpan and nearfield communication may also be supported when needed socs include analog interfaces including analogtodigital and digitaltoanalog converters often for signal processing these may be able to interface with different types of sensors or actuators including smart transducers they may interface with applicationspecific modules or shields or they may be internal to the soc such as if an analog sensor is built in to the soc and its readings must be converted to digital signals for mathematical processing digital signal processors digital signal processor dsp cores are often included on systemsonchip they perform signal processing operations in systemsonchip for sensors actuators data collection data analysis and multimedia processing dsp cores typically feature very long instruction word vliw and single instruction multiple data simd instruction set architectures and are therefore highly amenable to exploiting instructionlevel parallelism through parallel processing and superscalar execution4 dsp cores most often feature applicationspecific instructions and as such are typically applicationspecific instructionset processors asip such applicationspecific instructions correspond to dedicated hardware functional units that compute those instructions typical dsp instructions include multiplyaccumulate fast fourier transform fused multiplyadd and convolutions other as with other computer systems socs require timing sources to generate clock signals control execution of soc functions and provide time context to signal processing applications of the soc if needed popular time sources are crystal oscillators and phaselocked loops systemonchip peripherals including countertimers realtime timers and poweron reset generators socs also include voltage regulators and power management circuits intermodule communication systemsonchip comprise many execution units these units must often send data and instructions back and forth because of this all but the most trivial socs require communications subsystems originally as with other microcomputer technologies data bus architectures were used but recently designs based on sparse intercommunication networks known as networksonchip noc have risen to prominence and are forecast to overtake bus architectures for soc design in the near future busbased communication historically a shared global computer bus typically connected the different components also called blocks of the systemonchip a very common bus for systemonchip communications is arms royaltyfree advanced microcontroller bus architecture amba standard direct memory access controllers route data directly between external interfaces and soc memory bypassing the cpu or control unit thereby increasing the data throughput of the systemonchip this is similar to some device drivers of peripherals on componentbased multichip module pc architectures computer buses are limited in scalability supporting only up to tens of cores multicore on a single chipxiii networkonchip network on a chip in the late 2010s a trend of systemsonchip implementing communications subsystems in terms of a networklike topology instead of busbased protocols has emerged a trend towards more processor cores on socs has caused onchip communication efficiency to become one of the key factors in determining the overall system performance and costxiii networksonchip have advantages including destination and applicationspecific routing greater power efficiency and reduced possibility of bus contention networkonchip architectures take inspiration from networking protocols like tcp and the internet protocol suite for onchip communication although they typically have fewer network layers optimal networkonchip network architectures are an ongoing area of much research interest noc architectures range from traditional distributed computing network topologies such as torus hypercube meshes and tree networks to genetic algorithm scheduling to randomized algorithms such as random walks with branching and randomized time to live ttl many soc researchers consider noc architectures to be the future of systemonchip design because they have been shown to efficiently meet power and throughput needs of soc designs current noc architectures are twodimensional 2d ic design has limited floorplanning choices as the number of cores in socs increase so as threedimensional integrated circuits 3dics emerge soc designers look to build threedimensional onchip networks known as 3dnocs design flow electronics design flow physical design electronics and platformbased designsee also systems design and software design process systemonachip design flow a system on chip consists of both the hardware described in structure and the software controlling the microcontroller microprocessor or digital signal processor cores peripherals and interfaces the design flow for an soc aims to develop this hardware and software at the same time also known as architectural codesign the design flow must also take into account optimizations optimization goals and constraints most socs are developed from prequalified hardware component ip core specifications for the hardware elements and execution units collectively blocks described above together with software device drivers that may control their operation of particular importance are the protocol stacks that drive industrystandard interfaces like usb the hardware blocks are put together using computeraided design tools specifically electronic design automation tools the software modules are integrated using a software integrated development environment systemsonchip components are also often designed in highlevel programming languages such as c matlab or systemc and converted to rtl designs through highlevel synthesis hls tools such as c to hdl or flow to hdl other components can remain software and be compiled and embedded onto softcore processors included in the soc as modules in hdl as ip cores once the architecture of the soc has been defined any new hardware elements are written in an abstract hardware description language termed register transfer level rtl which defines the circuit behavior or synthesized into rtl from a high level language through highlevel synthesis these elements are connected together in a hardware description language to create the full soc design the logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called glue logic design verification further information functional verification and signoff electronic design automation chips are verified for logical correctness before being sent to a semiconductor foundry this process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle often quoted as 70 with the growing complexity of chips hardware verification languages like systemverilog systemc e and openvera are being used bugs found in the verification stage are reported to the designer traditionally engineers have employed simulation acceleration emulation or prototyping on reprogrammable hardware to verify and debug hardware and software for soc designs prior to the finalization of the design known as tapeout fieldprogrammable gate arrays fpgas are favored for prototyping systemsonchip because fpga prototypes are reprogrammable allow debugging and are more flexible than applicationspecific integrated circuits asics with high capacity and fast compilation time simulation acceleration and emulation are powerful technologies that provide wide visibility into systems both technologies however operate slowly on the order of mhz which may be significantly slower up to 100 times slower than the socs operating frequency acceleration and emulation boxes are also very large and expensive at over us1 million fpga prototypes in contrast use fpgas directly to enable engineers to validate and test at or close to a systems full operating frequency with realworld stimuli tools such as certus are used to insert probes in the fpga rtl that make signals available for observation this is used to debug hardware firmware and software interactions across multiple fpgas with capabilities similar to a logic analyzer in parallel the hardware elements are grouped and passed through a process of logic synthesis during which performance constraints such as operational frequency and expected signal delays are applied this generates an output known as a netlist describing the design as a physical circuit and its interconnections these netlists are combined with the glue logic connecting the components to produce the schematic description of the soc as a circuit which can be printed onto a chip this process is known as place and route and precedes tapeout in the event that the socs are produced as applicationspecific integrated circuits asic optimization goals systemsonchip must optimize power use area on die communication positioning for locality between modular units and other factors optimization is necessarily a design goal of systemsonchip if optimization was not necessary the engineers would use a multichip module architecture without accounting for the area utilization power consumption or performance of the system to the same extent common optimization targets for systemonchip designs follow with explanations of each in general optimizing any of these quantities may be a hard combinatorial optimization problem and can indeed be nphard fairly easily therefore sophisticated optimization algorithms are often required and it may be practical to use approximation algorithms or heuristics in some cases additionally most soc designs contain multiple variables to optimize simultaneously so pareto efficient solutions are sought after in soc design oftentimes the goals of optimizing some of these quantities are directly at odds further adding complexity to design optimization of systemsonchip and introducing tradeoffs in system design for broader coverage of tradeoffs and requirements analysis see requirements engineering targets power consumption systemsonchip are optimized to minimize the electrical power used to perform the socs functions most socs must use low power soc systems often require long battery life such as smartphones can potentially spending months or years without a power source needing to maintain autonomous function and often are limited in power use by a high number of embedded socs being networked together in an area additionally energy costs can be high and conserving energy will reduce the total cost of ownership of the soc finally waste heat from high energy consumption can damage other circuit components if too much heat is dissipated giving another pragmatic reason to conserve energy the amount of energy used in a circuit is the integral of power consumed with respect to time and the average rate of power consumption is the product of current by voltage equivalently by ohms law power is current squared times resistance or voltage squared divided by resistance p i v v 2 r i 2 r displaystyle pivfrac v2ri2r systemsonchip are frequently embedded in portable devices such as smartphones gps navigation devices digital watches including smartwatches and netbooks customers want long battery lives for mobile computing devices another reason that power consumption must be minimized in systemsonchip multimedia applications are often executed on these devices including video games video streaming image processing all of which have grown in computational complexity in recent years with user demands and expectations for higherquality multimedia computation is more demanding as expectations move towards 3d video at high resolution with multiple standards so socs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery3 performance per watt see also green computing socs are optimized to maximize power efficiency in performance per watt maximize the performance of the soc given a budget of power usage many applications such as edge computing distributed processing and ambient intelligence require a certain level of computational performance but power is limited in most soc environments the arm architecture has greater performance per watt than x86 in embedded systems so it is preferred over x86 for most soc applications requiring an embedded processor waste heat heat generation in integrated circuitssee also thermal management in electronics and thermal design power soc designs are optimized to minimize waste heat output on the chip as with other integrated circuits heat generated due to high power density are the bottleneck to further miniaturization of components29 in particular most socs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system because of high transistor counts on modern devices due to moores law oftentimes a layout of sufficient throughput and high transistor density is physically realizable from fabrication processes but would result in unacceptably high amounts of heat in the circuits volume1 these thermal effects force soc and other chip designers to apply conservative design margins creating less performant devices to mitigate the risk of catastrophic failure due to increased transistor densities as length scales get smaller each process generation produces more heat output than the last compounding this problem systemonchip architectures are usually heterogeneous creating spatially inhomogeneous heat fluxes which are cannot be effectively mitigated by uniform passive cooling1 throughput this section needs expansion you can help by adding to it october 2018 socs are optimized to maximize computational and communications throughput latency this section needs expansion you can help by adding to it october 2018 socs are optimized to minimize latency for some or all of their functions this can be accomplished by laying out elements with proper proximity and locality to eachother to minimize the interconnection delays and maximize the speed at which data is communicated between modules functional units and memories in general optimizing to minimize latency is an npcomplete problem equivalent to the boolean satisfiability problem for tasks running on processor cores latency and throughput can be improved with task scheduling some tasks run in applicationspecific hardware units however and even task scheduling may not be sufficient to optimize all softwarebased tasks to meet timing and throughput constraints methodologies further information multiobjective optimization multiplecriteria decision analysis and architecture tradeoff analysis this section needs expansion you can help by adding to it october 2018 systems on chip are modeled with standard hardware verification and validation techniques but additional techniques are used to model and optimize soc design alternatives to make the system optimal with respect to multiplecriteria decision analysis on the above optimization targets task scheduling task scheduling is an important activity in any computer system with multiple processes or threads sharing a single processor core it is important to reduce latency and increase throughput for embedded software running on an socs processor cores not every important computing activity in a systemonchip is performed in software running on onchip processors but scheduling can drastically improve performance of softwarebased tasks and other tasks involving shared resources socs often schedule tasks according to network scheduling and randomized scheduling algorithms pipelining for a broader coverage of this topic see pipeline computing hardware and software tasks are often pipelined in processor design pipelining is an important principle for speedup in computer architecture they are frequently used in gpus graphics pipeline and risc processors evolutions of the classic risc pipeline but are also applied to applicationspecific tasks such as digital signal processing and multimedia manipulations in the context of systemsonchip probabilistic modeling systemsonchip are often analyzed though probabilistic models queueing theory queueing networks and markov chains for instance littles law allows soc states and noc buffers to be modeled as arrival processes and analyzed through poisson random variables and poisson processes markov chains socs are often modeled with markov chains both discrete time and continuous time variants markov chain modeling allows asymptotic analysis of the systemonchips steady state distribution of power heat latency and other factors to allow design decisions to be optimized for the common case fabrication this section does not cite any sources please help improve this section by adding citations to reliable sources unsourced material may be challenged and removed march 2017 learn how and when to remove this template messagefurther information semiconductor device fabrication the netlists described above are used as the basis for the physical design place and route flow to convert the designers intent into the design of the soc throughout this conversion process the design is analyzed with static timing modeling simulation and other tools to ensure that it meets the specified operational parameters such as frequency power consumption and dissipation functional integrity as described in the register transfer level code and electrical integrity when all known bugs have been rectified and these have been reverified and all physical design checks are done the physical design files describing each layer of the chip are sent to the foundrys mask shop where a full set of glass lithographic masks will be etched these are sent to a wafer fabrication plant to create the soc dice before packaging and testing socs can be fabricated by several technologies including full custom asic standard cell asic fieldprogrammable gate array fpga asics consume less power and are faster than fpgas but cannot be reprogrammed and are expensive to manufacture fpga designs are more suitable for lower volume designs but after enough units of production asics reduce the total cost of ownership soc designs consume less power and have a lower cost and higher reliability than the multichip systems that they replace with fewer packages in the system assembly costs are reduced as well however like most verylargescale integration vlsi designs the total cost and higher nonrecurring engineering costs when it is not feasible to construct an soc for a particular application an alternative is a system in package sip comprising a number of chips in a single package when produced in large volumes soc is more costeffective than sip because its packaging is simpler another reasons sip may be preferred is waste heat may be too high in a systemonchip for a given purpose because functional components are too close together and in an sip heat will dissipate better from different functional modules being physically further apart benchmarks this section needs expansion you can help by adding to it october 2018 soc research and development often compares many options benchmarks such as cosmic are developed to help such evaluations list of systemonachip suppliers postsilicon validation arm architecture singleboard computer system in package network on a chip programmable systemonchip applicationspecific instruction set processor asip platformbased design lab on a chip organ on a chip in biomedical technology notes badawy wael jullien graham a eds 2003 systemonchip for realtime applications kluwer international series in engineering and computer science secs 711 boston kluwer academic publishers isbn9781402072543 oclc50478525 465 pages furber stephen b 2000 arm systemonchip architecture boston addisonwesley isbn0201675196 kundu santanu chattopadhyay santanu 2014 networkonchip the next generation of systemonchip integration 1st ed boca raton fl crc press isbn9781466565272 oclc895661009 socc annual ieee international soc conference baya free soc platform assembly and ip integration tool systems on chip for embedded applications auburn university seminar in vlsi vtesystems on chip socstypes network on a chip noc multiprocessor soc mpsoc programmable soc psoc microcontroller alternatives multichip module mcm system in package sip package on package pop related processor computing microprocessor core chronology embedded systems mobile computing processor design digital signal processor dsp vteprocessor technologiesmodels turing machine universal postturing quantum belt machine stack machine finitestate machine with datapath hierarchical queue automaton register machines counter pointer randomaccess randomaccess stored program architecture von neumann harvard modified dataflow transporttriggered cellular endianness memory access numa huma loadstore registermemory cache hierarchy memory hierarchy virtual memory secondary storage heterogeneous fabric multiprocessing cognitive neuromorphic instruction setarchitecturestypes cisc risc applicationspecific edge trips vliw epic misc oisc nisc zisc comparison addressing modes x86 arm mips power powerpc sparc itanium unicore microblaze riscv othersexecutioninstruction pipelining pipeline stall operand forwarding classic risc pipeline hazards data dependency structural control false sharing outoforder tomasulo algorithm reservation station reorder buffer register renaming speculative branch prediction memory dependence prediction parallelismlevel bit bitserial word instruction pipelining scalar superscalar task thread process data vector memory distributed multithreading temporal simultaneous hyperthreading speculative preemptive cooperative flynns taxonomy sisd simd swar simt misd mimd spmd processorperformance transistor count instructions per cycle ipc cycles per instruction cpi instructions per second ips floatingpoint operations per second flops transactions per second tps synaptic updates per second sups performance per watt ppw cache performance metrics computer performance by orders of magnitude types central processing unit cpu graphics processing unit gpu gpgpu vector barrel stream coprocessor asic fpga cpld multichip module mcm system in package sip by application microprocessor microcontroller mobile notebook ultralowvoltage asip systemson chip systemonchip soc multiprocessor mpsoc programmable psoc networkonchip noc hardwareaccelerators ai accelerator vision processing unit vpu physics processing unit ppu digital signal processor dsp tensor processing unit tpu secure cryptoprocessor network processor baseband processor word size 1bit 2bit 4bit 8bit 16bit 32bit 48bit 64bit 128bit 256bit 512bit others variable core count singlecore multicore manycore heterogeneous architecture components core cache cpu cache replacement policies coherence bus clock rate fifo functional units arithmetic logic unt alu address generation unit agu floatingpoint unit fpu memory management unit loadstore unit translation lookaside buffer tlb logic combinational sequential glue logic gate quantum array registers processor register register file memory buffer program counter stack control unit instruction unit data buffer write buffer microcode rom counter datapath multiplexer demultiplexer adder multiplier cpu binary decoder address decoder sum addressed decoder barrel shifter circuitry integrated circuit 3d mixed signal power management boolean digital analog quantum switch powermanagement pmu apm acpi dynamic frequency scaling dynamic voltage scaling clock gating performance per watt ppw related history of generalpurpose cpus microprocessor chronology processor design digital electronics hardware security module vtesingleboard computer singleboard microcontrollerdevices arduino arndale board asus tinker board banana pi beagleboard cotton candy chip cubieboard dragonboard edison galileo gumstix hawkboard igepv2 nvidia drive nvidia jetson odroid olinuxino pandaboard pine64 parallella rascal raspberry pi snowball tivac launchpad udoo socsarm allwinner ax exynos imx k3v3 mt nomadik novathor omap rockchip qualcomm snapdragon tegra wondermedia mips jz x86x8664 atom jaguarbased pumabased quark software apache hadoop linaro comparison of singleboard computers vteprogrammable logicconcepts asic soc fpga logic block cpld epld pla pal gal psoc reconfigurable computing xputer soft microprocessor circuit underutilization highlevel synthesis hardware acceleration languages verilog a ams vhdl ams vital systemverilog dpi systemc ahdl handelc psl upf palasm abel cupl openvera c to hdl flow to hdl myhdl jhdl ella companies accellera actel achronix amd aldec atmel cadence cypress duolog forte intel altera lattice national mentor graphics microsemi signetics synopsys magma virage logic texas instruments tabula xilinx productshardware ice stratix virtex software altera quartus xilinx ise xilinx vivado modelsim vtr simulators ipproprietary arc arm cortexm leon latticemico8 microblaze picoblaze nios nios ii opensource jop latticemico32 opencores openrisc 1200 riscv zet vtemajor fields of computer sciencenote this template roughly follows the 2012 acm computing classification systemhardware printed circuit board peripheral integrated circuit very large scale integration systems on chip socs energy consumption green computing electronic design automation hardware acceleration computer systemsorganization computer architecture embedded system realtime computing dependability networks network architecture network protocol network components network scheduler network performance evaluation network service software organization interpreter middleware virtual machine operating system software quality software notationsand tools programming paradigm programming language compiler domainspecific language modeling language software framework integrated development environment software configuration management software library software repository software development software development process requirements analysis software design software construction software deployment software maintenance programming team opensource model theory of computation model of computation formal language automata theory computational complexity theory logic semantics algorithms algorithm design analysis of algorithms algorithmic efficiency randomized algorithm computational geometry mathematicsof computing discrete mathematics probability statistics mathematical software information theory mathematical analysis numerical analysis informationsystems database management system information storage systems enterprise information system social information systems geographic information system decision support system process control system multimedia information system data mining digital library computing platform digital marketing world wide web information retrieval security cryptography formal methods security services intrusion detection system hardware security network security information security application security humancomputerinteraction interaction design social computing ubiquitous computing visualization accessibility concurrency concurrent computing parallel computing distributed computing multithreading multiprocessing artificialintelligence natural language processing knowledge representation and reasoning computer vision automated planning and scheduling search methodology control method philosophy of artificial intelligence distributed artificial intelligence machine learning supervised learning unsupervised learning reinforcement learning multitask learning crossvalidation graphics animation rendering image manipulation graphics processing unit mixed reality virtual reality image compression solid modeling appliedcomputing ecommerce enterprise software computational mathematics computational physics computational chemistry computational biology computational social science computational engineering computational healthcare digital art electronic publishing cyberwarfare electronic voting video games word processing operations research educational technology document management book category portal wikiproject commons vtehardware accelerationtheory universal turing machine parallel computing distributed computing applications gpu gpgpu directx audio digital signal processing hardware random number generation artificial intelligence cryptography ssl machine vision custom hardware attack scrypt networking implementations highlevel synthesis c to hdl fpga asic cpld system on chip network on chip architectures data flow transport triggered multicore manycore heterogeneous inmemory computing systolic array neuromorphic related programmable logic processor design chronology digital electronics virtualization hardware emulation logic synthesis embedded systems 